This invention relates to a semiconductor device. In particular, this invention relates to a semiconductor device comprising a semiconductor substrate and a bipolar transistor on the semiconductor substrate.
In the field of data communications, there is an ongoing need for power amplifiers that are able to operate at high speed. Systems of this kind typically use power amplifiers at the transmitter side to enable them to transfer the data from the circuit to the open field by electro-magnetic radiation. These high-frequency power amplifiers are designed to work at high currents and/or high voltages in order to transmit sufficient power.
Although CMOS based technologies can be used to produce high power output power amplifiers, bipolar technologies remain important for providing high-efficiency, high power amplifiers at (ultra-) high frequencies. There is often a trade-off in bipolar devices between high power performance, high frequency performance and cost.
For bipolar technologies, high currents can be obtained with large-area transistors, while the breakdown voltage of the device largely determines the maximum voltage swing during operation. Optimal RF performance (e.g. maximum oscillation frequency, fMAX) however, can only be obtained with narrow emitter transistors such that the intrinsic base resistance is minimal. Therefore, long “finger”-like transistor shapes are often used to increase the transistor area, transistor current and corresponding output power. It is common practice now to divide the active area into several emitter fingers in order to spread the total current of the transistor across more area.
FIG. 1A schematically illustrates an example of bipolar transistor as is known in the art. The transistor includes a collector 4, a base 6 and an emitter 8. The base 6 is located on (above) the collector 4 (which may, for example, be buried in a semiconductor substrate upon which the device is located), and in turn the emitter 8 is located on (above) the base 6. The collector 4, base 6 and emitter 8 are each provided with respective contacts 14, 16 and 18 for making electrical connection thereto.
In devices of this kind, the maximum oscillation frequency figure of merit fMAX is dominated by two factors, namely the base resistance (RB) and collector-base capacitance (CBC), as can be seen from the simplified formula:fMAX∝√{square root over (fT/CBCRB)}  (1)where fT is the cut off frequency (see “A Novel SOI Lateral Bipolar Transistor with 30 GHz fMAX and 27V BVCEO for RF Power Amplifier Applications”, Proceedings of the 17th International Symposium on Power Semiconductor Devices & IC's, May 23-26, 2005, Santa Barbara, Calif.).
Measures to improve fMAX of a bipolar transistor include the reduction of RB (both intrinsic and extrinsic) by increasing the doping level in the base or by modifying the extrinsic base region. However, increasing the doping level in the intrinsic base can result in a lower collector current and can consequently lower fT.
Another approach to improve fMAX involves attempting to reduce the collector-base capacitance CBC. In the past, these efforts have included changing the device architecture or by reducing overlays (e.g. using better lithographic techniques).
One particular approach to reducing CBC has included inverting the design of the transistor (with respect to the schematic example shown in FIG. 1A) to produce a so called “bottom-up transistor” (see, for example, “Single and Double Heterojunction Bipolar Transistors in Collector-up Topology”, A. Henkel et al., GAAS 98, Amsterdam, and “Collector-up SiGe Heterojunction Bipolar Transistors”, A. Gruhle et al., IEEE Transactions on Electron Devices, vol. 46, No. 7, July 1999).
A schematic of a bottom-up bipolar transistor is illustrated in FIG. 1B. As in the example of FIG. 1A, the transistor includes a collector 4, a base 6 and an emitter 8. Again, the collector 4, base 6 and emitter 8 are each provided with respective contacts 14, 16 and 18 for making electrical connection thereto. However, in the bottom-up topology, the base 6 is located on (above) the emitter 8, while the collector 4 is located on (above) the base 6.
By comparison of FIGS. 1A and 1B, it can be seen that in the bottom-up approach, the contact area between the collector 4 and the base 6 is relatively small as compared to the more conventional design in which the base-collector contact area is defined by the area of the base 6. This results in a smaller collector-base capacitance CBC.
Conversely, the contact area between the base 6 and the emitter 8 in FIG. 1B is relatively large. Hence, the reduction in collector-base capacitance comes at a cost, namely an increased base emitter capacitance CBE, which in turn lowers fT performance hampering the overall effort to improve fMAX (equation 1).
Accordingly, the bottom-up bipolar transistor concept may allow improvements in fMAX (it is thought the benefit from reduced CBC can outweigh the effects of an increased CBE). Embodiments of this invention can further improve upon the performance of a bipolar transistor in which the base is located above the emitter and the collector is located above the base.